For example, U.S. Pat. No. 5,753,529, JP-2008-166705A corresponding to US 2008/0135832, and JP-2008-263135A disclose a semiconductor chip having multiple electrodes on both sides.
FIG. 12 illustrates a cross-sectional view of a semiconductor chip 10 disclosed in US 2008/0135832.
In the semiconductor chip, multiple devices including active devices 31-33, 41-43 and passive devices 51-52 are formed in a semiconductor substrate 20. The active device 31 is a bipolar transistor, the active device 32 is a complementary metal-oxide semiconductor (CMOS) transistor, the active device 33 is a lateral MOS transistor, the active device 41 is a vertical MOS transistor, the active device 42 is an insulated gate bipolar transistor (IGBT), and the active device 43 is a diode. The passive device 51 is a N−-type device acting as a resistor, and the passive device 52 is a N+-type device acting as a wire.
The semiconductor substrate 20 is a N−-type bulk single crystal silicon. Each of the active devices 31-33, 41-43 and passive devices 51-52 is not a thin-film device, but is integrated in the semiconductor substrate 20. The semiconductor substrate 20 is divided by insulation regions T into field regions F1-F8. The insulation regions T penetrate the semiconductor substrate 20, and each of the field regions F1-F8 is surrounded by the insulation regions T. The active devices 31-33, 41-43 and passive devices 51-52 are formed in the field regions F1-F8, respectively. As can be seen from FIG. 12, each of the active devices 31-33 has an electrode dr1 on a first side S1 of the semiconductor substrate 20. The active devices 31-33 are herein defined as “single-sided electrode devices”. In contrast, each of the active devices 41-43 and the passive devices 51-52 has the electrode dr1 on the first side S1 and an electrode dr2 on a second side S2 of the semiconductor substrate 20. The active devices 41-43 and the passive devices 51-52 are herein defined as “double-sided electrode devices”.
Since the semiconductor chip 10 shown in FIG. 12 can include a double-sided electrode device such as the vertical MOS transistor 41 or the IGBT 42, the semiconductor chip 10 can be used as a power semiconductor device. Further, since the semiconductor chip 10 employs a bulk single crystal silicon substrate as the semiconductor substrate 20, the double-side electrode device formed in the semiconductor substrate 20 can be resistant to a large current and a surge such as electrostatic discharge (ESD). Furthermore, since the semiconductor substrate 20 has no buried insulation layer, radiation performance of the semiconductor chip 10 can be increased to greater than that of a semiconductor chip that employs a silicon-on-insulator (SOI) substrate.
As described above, the semiconductor chip 10 has the electrodes dr1, dr2 on both sides. Such a semiconductor chip is herein defined as a “double-sided multi-electrode chip”. A special structure is required to mount the double-sided multi-electrode chip to a semiconductor device.
JP-2008-263135A discloses a structure for mounting a double-sided multi-electrode chip to a silicon substrate having an electrode pattern corresponding to backside electrodes of the double-sided multi-electrode chip. JP-2008-263135A further discloses a structure for mounting the double-sided multi-electrode chip to a lead frame having through holes corresponding to the backside electrodes of the double-sided multi-electrode chip. In the structures, connection to front-side electrodes of the double-sided multi-electrode chip is performed by using a wire bonding method or a ribbon bonding method. However, it is difficult to use a wire bonding method or a ribbon bonding method, because the double-sided multi-electrode chip has electrodes on both sides. Further, when the double-sided multi-electrode chip is thin, it is likely that the double-sided multi-electrode chip is broken during manufacturing processes such as a bonding process and a resin molding process.